SH7706 Datasheet, PDF (600/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 20 D/A Converter (DAC)
20.4 Operation
The D/A converter has two built-in D/A conversion circuits that can perform conversion
independently.
D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value
is modified, conversion of the new data begins immediately. The conversion results are output
when bits DAOE0 and DAOE1 are set to 1.
An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 20.2.
1. Data to be converted is written in DADR0.
2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA0 becomes an output pin. The
converted result is output after the conversion time. The output value is (DADR0 contents/256)
× AVcc. Output of this conversion result continues until the value in DADR0 is modified or
the DAOE0 bit is cleared to 0.
3. If the DADR0 value is modified, conversion starts immediately, and the result is output after
the conversion time.
4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin.
DADR0
write cycle
DACR
write cycle
DADR0
write cycle
DACR
write cycle
φ
Address bus
DADR0
Conversion data 1
Conversion data 2
DAOE0
DA0
High-impedance state
Legend:
t_DCONV: D/A conversion time
t_DCONV
Conversion
result 1
Conversion
result 2
t_DCONV
Figure 20.2 Example of D/A Converter Operation
Rev. 5.00 May 29, 2006 page 552 of 698
REJ09B0146-0500