SH7706 Datasheet, PDF (422/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
Bit Bit Name Initial Value R/W Description
3
MPIE
0
R/W Multiprocessor Interrupt Enable
Enables or disables multiprocessor interrupts. The
MPIE setting is used only in the asynchronous mode,
and only if the multiprocessor mode bit (MP) in the
serial mode register (SCSMR) is set to 1 during
reception. The MPIE setting is ignored in the clock
synchronous mode or when the MP bit is cleared to 0.
0: Multiprocessor interrupts are disabled (normal
receive operation)
[Clearing conditions]
1. MPIE is cleared to 0.
2. MPB = 1 is in received data.
1: Multiprocessor interrupts are enabled
Receive-data-full interrupt requests (RXI), receive-
error interrupt requests (ERI), and setting of the
RDRF, FER, and ORER status flags in the serial
status register (SCSSR) are disabled until data with a
multiprocessor bit of 1 is received.
Note:
The SCI does not transfer receive data from the
SCRSR to the SCRDR, does not detect receive
errors, and does not set the RDRF, FER, and
ORER flags in the serial status register
(SCSSR). When it receives data that includes
MPB = 1, the SCSSR's MPB flag is set to 1, and
the SCI automatically clears MPIE to 0,
generates RXI and ERI interrupts (if the TIE and
RIE bits in the SCSCR are set to 1), and allows
the FER and ORER bits to be set.
2
TEIE
0
R/W Transmit-End Interrupt Enable
Enables or disables the transmit-end interrupt (TEI)
requested if SCTDR does not contain new transmit
data when the MSB is transmitted.
0: Transmit-end interrupt (TEI) requests are disabled*
1: Transmit-end interrupt (TEI) requests are enabled*
Note: * The TEI request can be cleared by reading the
TDRE bit in SCSSR after it has been set to 1,
then clearing TDRE to 0 and clearing the TEND
bit to 0, or by clearing the TEIE bit to 0.
Rev. 5.00 May 29, 2006 page 374 of 698
REJ09B0146-0500