SH7706 Datasheet, PDF (369/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 11 Watchdog Timer (WDT)
11.3.4 Using Interval Timer Mode
When operating in interval timer mode, interval timer interrupts are generated at every overflow of
the counter. This enables interrupts to be generated at set periods.
1. Clear the WT/IT bit in the WTCSR register to 0, set the type of count clock in the CKS2 to
CKS0 bits, and set the initial value of the counter in the WTCNT counter.
2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode.
3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval
timer interrupt request is sent to INTC. The counter then resumes counting.
Rev. 5.00 May 29, 2006 page 321 of 698
REJ09B0146-0500