SH7706 Datasheet, PDF (359/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 10 Clock Pulse Generator (CPG)
Bit
Bit Name Initial Value R/W Description
14
IFC2
0
R/W CPU Clock Frequency Division Ratio
3
IFC1
0
2
IFC0
0
R/W These bits specify the frequency division ratio
R/W ^{(Divider 1) of the CPU clock with respect to the}
output frequency of PLL circuit 1.
000: × 1
001: × 1/2
100: × 1/3
010: × 1/4
Other than the above: Reserved (Setting prohibited)
Note: Do not set the CPU clock frequency lower
than the CKIO frequency.
13
PFC2
0
R/W Peripheral Clock Frequency Division Ratio
1
PFC1
0
0
PFC0
0
R/W These bits specify the division ratio (Divider 2)of the
R/W ^{peripheral clock frequency with respect to the}
frequency of the output frequency of PLL circuit 1 or
the frequency of the CKIO pin.
000: × 1
001: × 1/2
100: × 1/3
010: × 1/4
101: × 1/6
Other than the above: Reserved (Setting prohibited)
Note: Do not set the peripheral clock frequency
higher than the frequency of the CKIO pin.
12 to 9, —
0
7, 6
R
Reserved
These bits are always read as 0. The write value
should always be 0.
8
—
0
R
Reserved
This bit is always read as 1. The write value should
always be 1.
Note: Take enough care because the positions of the bits are not continuous.
Rev. 5.00 May 29, 2006 page 311 of 698
REJ09B0146-0500