SH7706 Datasheet, PDF (341/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
9.5.2 Register Description
The CMT has the following registers. Refer to section 23, List of Registers, for more details of the
addresses and access sizes.
• Compare match timer start register (CMSTR)
• Compare match timer control/status register (CMCSR)
• Compare match counter (CMCNT)
• Compare match constant register (CMCOR)
Compare Match Timer Start Register (CMSTR)
The compare match timer start register (CMSTR) is a 16-bit register that selects whether to
operate or halt the channel 0 and channel 1 counter (CMCNT).
Bit
15 to 2
1
0
Bit Name
—
—
STR0
Initial Value R/W
All 0
R
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
This bit can be read or written. Write 0 when writing.
Count start 0
Selects whether to operate or halt compare match
timer counter 0.
0: CMCNT0 count operation halted
1: CMCNT0 count operation
Rev. 5.00 May 29, 2006 page 293 of 698
REJ09B0146-0500