SH7706 Datasheet, PDF (13/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Item
8.5.4 Synchronous
DRAM Interface
Figure 8.27
Synchronous DRAM
Mode Write Timing
9.3.2 DMA
Destination Address
Registers 0 to 3
(DAR_0 to DAR_3)
Page
233
255
Revision (See Manual for Details)
Figure amended and note added
TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4
CKIO
A15 to A13
or (A14 to A12)*
A11 (A10)*
A12 (A11)*
A10 to A2
(A9 to A1)*
CSn
RD/WR
RASU or RASL
CASU or CASL
D31 to D0
CKE
(High)
Note: * Items in parentheses ( ) apply to 16-bit bus width connections.
Description amended
To transfer data in 16 bits or in 32 bits, specify the address with
16-bit or 32-bit address boundary. When transferring data in 16-
byte units, a 16-byte boundary (address 16n) must be set for
the source address value. Specifying other addresses does not
guarantee operation.
Rev. 5.00 May 29, 2006 page xiii of xlviii