SH7706 Datasheet, PDF (303/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
Channel 2
• DMA source address register 2 (SAR2)
• DMA destination address register 2 (DAR2)
• DMA transfer count register 2 (DMATCR2)
• DMA channel control register 2 (CHCR2)
Channel 3
• DMA source address register 3 (SAR3)
• DMA destination address register 3 (DAR3)
• DMA transfer count register 3 (DMATCR3)
• DMA channel control register 3 (CHCR3)
Any Channel
• DMA operation register (DMAOR)
9.3.1 DMA Source Address Registers 0 to 3 (SAR_0 to SAR_3)
DMA source address registers 0 to 3 (SAR_0 to SAR_3) are 32-bit read/write registers that
specify the source address of a DMA transfer. These registers include count functions, and during
a DMA transfer, these registers indicate the next source address.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the
source address value. Specifying other addresses does not guarantee operation.
The initial value is undefined by resets. The previous value is held in standby mode.
When accessed in 16 bits, the other 16-bit data which has not been accessed is held.
9.3.2 DMA Destination Address Registers 0 to 3 (DAR_0 to DAR_3)
DMA destination address registers 0 to 3 (DAR_0 to DAR_3) are 32-bit read/write registers that
specify the destination address of a DMA transfer. These registers include count functions, and
during a DMA transfer, these registers indicate the next destination address.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the
source address value. Specifying other addresses does not guarantee operation.
The initial value is undefined by resets. The previous value is held in standby mode.
When accessed in 16 bits, the other 16-bit data which has not been accessed is held.
Rev. 5.00 May 29, 2006 page 255 of 698
REJ09B0146-0500