SH7706 Datasheet, PDF (126/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 3 Memory Management Unit (MMU)
Both reading and writing use the longword of the data array specified by the entry address and
way number. The access size of the data array is fixed at longword.
(1) TLB Address Array Access
Read access
31
24 23
Address field
11110010
*
31
Data field
VPN
17 16 12 11 10 9 8 7 6
0
* VPN * * W 0 *
*
17 16 12 11 10 9 8 7
0
0
0 VPN 0 V
ASID
Write access
31
24 23
17 16 12 11 10 9 8 7 6
0
Address field
11110010
*
* ^VPN * * ^{W 0} *
*
31
17 16 12 11 10 9 8 7
0
Data field
VPN
*
* ^VPN * ^V
ASID
Legend
VPN: Virtual page number
ASID: Address space identifier
V: Valid bit
* : Don't care
W: Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
(2) TLB Data Array Access
Read/write access
31
24 23
17 16 12 11 10 9 8 7
0
Address field
11110011
*
* VPN * * W *
*
31 29 28
Data field 000
PPN
10 9 8 7 6 5 4 3 2 1 0
X V X PR SZ C D SH X
Legend:
PPN: Physical page number
V: Valid bit
PR: Protection key field
SZ: Page-size bit
C: Cacheable bit
D: Dirty bit
SH: Share status bit
*: Don't care
VPN: Virtual page number
X: 0 for read, don't care bit for write
W: Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
Figure 3.13 Specifying Address and Data for Memory-Mapped TLB Access
Rev. 5.00 May 29, 2006 page 78 of 698
REJ09B0146-0500