SH7706 Datasheet, PDF (87/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 2 CPU
Table 2.7 lists the logic operation instructions.
Table 2.7 Logic Operation Instructions
Instruction
Operation
Code
Privileged
Mode
Cycles T Bit
AND Rm,Rn
Rn & Rm → Rn
0010nnnnmmmm1001 —
1
—
AND #imm,R0
R0 & imm → R0
11001001iiiiiiii —
1
—
AND.B #imm,@(R0,GBR) (R0 + GBR) & imm →
(R0 + GBR)
11001101iiiiiiii —
3
—
NOT Rm,Rn
~Rm → Rn
0110nnnnmmmm0111 —
1
—
OR Rm,Rn
Rn | Rm → Rn
0010nnnnmmmm1011 —
1
—
OR #imm,R0
R0 | imm → R0
11001011iiiiiiii —
1
—
OR.B #imm,@(R0,GBR) (R0 + GBR) | imm →
(R0 + GBR)
11001111iiiiiiii —
3
—
TAS.B @Rn*
If (Rn) is 0, 1 → T;
1 → MSB of (Rn)*
0100nnnn00011011 —
4
Test
result
TST Rm,Rn
Rn & Rm; if the result
is 0, 1 → T
0010nnnnmmmm1000 —
1
Test
result
TST #imm,R0
R0 & imm; if the result 11001000iiiiiiii —
is 0, 1 → T
1
Test
result
TST.B #imm,@(R0,GBR) (R0 + GBR) & imm;
11001100iiiiiiii —
if the result is 0, 1 → T
3
Test
result
XOR Rm,Rn
Rn ^ Rm → Rn
0010nnnnmmmm1010 —
1
—
XOR #imm,R0
R0 ^ imm → R0
11001010iiiiiiii —
1
—
XOR.B #imm,@(R0,GBR) (R0 + GBR) ^ imm →
(R0 + GBR)
11001110iiiiiiii —
3
—
Note: * The on-chip DMAC's bus cycle is not inserted between the read and write cycles of the
TAS instruction. The bus authority is not released by the BREQ.
Rev. 5.00 May 29, 2006 page 39 of 698
REJ09B0146-0500