SH7706 Datasheet, PDF (372/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 12 Timer Unit (TMU)
Pφ
TCLK
RTCCLK
TUNI0
Prescaler
Clock
controller
Ch. 0
Counter
controller
Interrupt
controller
Ch. 1
Counter
controller
TOCR
TSTR
TCR_0
TCNT_0
TCOR_0
Bus interface
TCR_1
TCNT_1
TUNI1
Interrupt
controller
Ch. 2
Counter
controller
TCOR_1
TCR_2
TCPR_2
TCNT_2
TUNI2
TICPI2
Interrupt
controller
TCOR_2
TMU
Legend:
TOCR: Timer output control register
TSTR: Timer start register
TCR_n: Timer control register
Note: n: 0, 1, 2
TCNT_n: 32-bit timer counter
TCOR_n: 32-bit timer constant register
TCPR_2: 32-bit input capture register
Figure 12.1 TMU Block Diagram
Rev. 5.00 May 29, 2006 page 324 of 698
REJ09B0146-0500