SH7706 Datasheet, PDF (185/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
Item
Number of States
Peripheral
NMI
IRQ
IRL
Modules
Notes
Response Total
time
(5.5 + X)
× Icyc
+ 1.5 × Bcyc
Minimum 7
case
Maximum 10.5 + S
case
(6.5 + X)
× Icyc
+ 0.5 × Bcyc
+ 2 × Pcyc^*4
9
15.5 + S
(5.5 + X)
× Icyc
+ 0.5 × Bcyc
+ 3.5 × Pcyc
9.5
20.5 + S
(5.5 + X)
× Icyc
+ 1.5 × Pcyc^*3
(5.5 + X)
× Icyc
+ 3 × Pcyc^*4
7^*3/8.5^*4
Iφ:Bφ:Pφ = 1:1:1
10.5 + S^*3
16.5 + S^*4
Iφ:Bφ:Pφ = 4:1:1
Icyc: Duration of one cycle of Iφ.
Bcyc: Duration of one cycle of Bφ.
Pcyc: Duration of one cycle of Pφ.
Notes: 1. S also includes the memory access wait time.
The processing requiring the maximum execution time is LDC.L @Rm+, SR. When the
memory access is a cache-hit, this requires seven instruction execution cycles. When
the external access is performed, the corresponding number of cycles must be added.
There are also instructions that perform two external memory accesses; if the external
memory access is slow, the number of instruction execution cycles will increase
accordingly.
2. Edge detection.
3. Extended modules: TMU, RTC, SCI, WDT, REFC
4. Extended modules: DMAC, ADC, SCIF
Rev. 5.00 May 29, 2006 page 137 of 698
REJ09B0146-0500