SH7706 Datasheet, PDF (23/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Contents
Section 1 Overview ............................................................................................................. 1
1.1 Feature .............................................................................................................................. 1
1.2 Block Diagram .................................................................................................................. 3
1.3 Pin Assignment ................................................................................................................. 4
1.4 Pin Function ...................................................................................................................... 6
Section 2 CPU ...................................................................................................................... 13
2.1 Register Description.......................................................................................................... 13
2.1.1 Privileged Mode and Banks ................................................................................. 13
2.1.2 General Registers ................................................................................................. 15
2.1.3 System Registers.................................................................................................. 16
2.1.4 Control Registers ................................................................................................. 17
2.2 Data Formats..................................................................................................................... 20
2.2.1 Data Format in Registers...................................................................................... 20
2.2.2 Data Format in Memory....................................................................................... 20
2.3 Instruction Features........................................................................................................... 21
2.3.1 Execution Environment ....................................................................................... 21
2.3.2 Addressing Modes ............................................................................................... 23
2.3.3 Instruction Formats .............................................................................................. 27
2.4 Instruction Set ................................................................................................................... 30
2.4.1 Instruction Set Classified by Function ................................................................. 30
2.4.2 Instruction Code Map .......................................................................................... 46
2.5 Processor States and Processor Modes.............................................................................. 49
2.5.1 Processor States ................................................................................................... 49
2.5.2 Processor Modes .................................................................................................. 50
Section 3 Memory Management Unit (MMU) ........................................................... 51
3.1 Role of MMU.................................................................................................................... 51
3.1.1 This LSI's MMU .................................................................................................. 53
3.2 Register Description.......................................................................................................... 56
3.2.1 Page Table Entry Register High (PTEH) ............................................................. 57
3.2.2 Page Table Entry Register Low (PTEL) .............................................................. 57
3.2.3 The Translation Table Base Register (TTB) ........................................................ 58
3.2.4 The TLB Exception Address Register (TEA) ...................................................... 58
3.2.5 MMU Control Register (MMUCR) ..................................................................... 58
3.3 TLB Functions .................................................................................................................. 60
3.3.1 Configuration of the TLB .................................................................................... 60
3.3.2 TLB Indexing....................................................................................................... 62
Rev. 5.00 May 29, 2006 page xxiii of xlviii