SH7706 Datasheet, PDF (186/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
Interrupt
acceptance
Start of interrupt
processing
0.5 × Icyc
+ 0.5 × Bcyc
+ 3.5 × Pcyc
IRL
5 × Icyc
Instruction (instruction
replaced by interrupt
exception processing)
Overrun fetch
First instruction of interrupt
handler
IF ID EX EX EX EX
IF
IF ID EX
Legend:
IF: Instruction fetch: Instruction is fetched from memory in which program is stored.
ID: Instruction decode: Fetched instruction is decoded.
EX: Instruction execution: Data operation and address calculation are performed in
accordance with result of decoding.
Figure 6.4 Example of Pipeline Operations when IRL Interrupt Is Accepted
Rev. 5.00 May 29, 2006 page 138 of 698
REJ09B0146-0500