SH7706 Datasheet, PDF(143/749 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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SH7706 Datasheet, PDF (143/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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Section 4 Exception Processing

C. When a privileged instruction in a delay slot is decoded in user mode

Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR

with LDC/STC are not privileged instructions.

ï£§ Operations: The PC of the previous delay branch instruction is saved to the SPC. SR of the

instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT. The BL,

MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. When an

undefined instruction other than H'Fxxx is decoded, operation cannot be guaranteed.

â¢ User break point trap

ï£§ Conditions: When a break condition set in the user break point controller is satisfied

ï£§ Operations: When a post-execution break occurs, the PC of the instruction immediately

after the instruction that set the break point is set in the SPC. If a pre-execution break

occurs, the PC of the instruction that set the break point is set in the SPC. SR when the

break occurs is set in SSR. H'1E0 is set in EXPEVT. The BL, MD, and RB bits in SR are

set to 1 and a branch occurs to PC = VBR + H'0100. See section 7, User Break Controller,

for more information.

â¢ DMA Address error

ï£§ Conditions: When corresponded to the following items.

A. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)

B. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,

4n + 3)

ï£§ Operations: The PC of the instruction immediately after the instruction executed before the

exception occurs is saved to the SPC. SR when the exception occurs is saved to SSR.

H'5C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs

to PC = VBR + H'0100.

4.4.3 Interrupts

â¢ NMI

ï£§ Conditions: NMI pin edge detection

ï£§ Operations: The PC and SR after the instruction that receives the interrupt are saved to the

SPC and SSR, respectively. H'01C0 is set to INTEVT and INTEVT2. The BL, MD, and

RB bits of the SR are set to 1 and a branch occurs to PC = VBR + H'0600. This interrupt is

not masked by SR.IMASK and received with top priority when the SR's BL bit in SR is 0.

When the BL bit is 1, the interrupt is masked. When BLMSK in ICRI is a logic zero and

not masked when BLMSK in ICRI is a logic one. See section 6, Interrupt Controller

(INTC), for more information.

Rev. 5.00 May 29, 2006 page 95 of 698

REJ09B0146-0500

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