SH7706 Datasheet, PDF (495/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.5 Serial Mode Register 2 (SCSMR2)
The serial mode register2 (SCSMR2) is an eight-bit register that specifies the SCIF serial
communication format and selects the clock source for the baud rate generator.
The CPU can always read and write the SCSMR2.
Initial
Bit Bit Name Value R/W Description
7
—
0
R
Reserved
This bit is always read 0. The write value should always be
0.
6
CHR
0
R/W Character Length
Selects seven-bit or eight-bit data in the asynchronous
mode.
0: Eight-bit data.
1: Seven-bit data.
Note: When seven-bit data is selected, the MSB (bit 7)
in SCFTPR2 is not transmitted.
5
PE
0
R/W Parity Enable
Selects whether to add a parity bit to transmit data and to
check the parity of receive data.
0: Parity bit not added or checked.
1: Parity bit added and checked.
Note: When PE is set to 1, an even or odd parity bit is
added to transmit data, depending on the parity mode
(O/E) setting. Receive data parity is checked according
to the even/odd (O/E) mode setting.
Rev. 5.00 May 29, 2006 page 447 of 698
REJ09B0146-0500