SH7706 Datasheet, PDF (584/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 19 A/D Converter (ADC)
19.3.3 A/D Control Register (ADCR)
ADCR is an 8-bit read/write register that enables or disables external triggering of A/D
conversion. ADCR is initialized to H'07 by a reset and in standby mode.
Bit
7
6
5
4, 3
2 to 0
Bit Name Initial Value R/W Description
TRGE1 0
R/W Trigger Enable
TRGE0 0
R/W Enables or disables external triggering of A/D
conversion.
00: When an external trigger is input, the A/D
conversion does not start
01: The same as above
10: The same as above
11: The A/D conversion starts at the falling edge of
an input signal from the external trigger pin
(ADTRG).
SCN
0
R/W Scan Mode
Selects multi mode or scan mode when the MULTI
bit is set to 1. See the description of bit 4 in 19.3.2,
A/D Control/Status Register (ADCSR).
—
All 0
R/W Reserved
These bits are always read as 0. The write value
should always be 0.
—
All 1
R
Reserved
These bits are always read as 1. The write value
should always be 0.
19.4 Bus Master Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the bus master by the upper 8
bits of the 16-bit peripheral data bus. Therefore, although the upper byte can be accessed directly
by the bus master, the lower byte is read through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the bus master and the lower-byte value is transferred into TEMP. Next,
when the lower byte is read, the TEMP contents are transferred to the bus master.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, the read value is not guaranteed.
Rev. 5.00 May 29, 2006 page 536 of 698
REJ09B0146-0500