SH7706 Datasheet, PDF (158/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 5 Cache
(1) Address array access
Address specification
Read access
31
24 23
14 13 12 11
4 32
1111 0000 *^{…………}* W
Entry address 0 *
0
00
Write access
31
24 23
14 13 12 11
4 32
0
1111 0000 *^{…………}* W
Entry address A _{* 0 0}
Data specification (both read and write accesses)
313029
0 0 0 Address tag (28–10)
10 9
4
LRU
32
XX
10
UV
(2) Data array access (both read and write accesses)
Address specification
31
24 23
14 13 12 11
4 3 21 0
1111 0001 _*…………_* W
Entry address
L0 0
Data specification
31
0
Longword
Legend:
X: 0 for read, don't care for write
*: Don't care
Figure 5.4 Specifying Address and Data for Memory-Mapped Cache Access
Rev. 5.00 May 29, 2006 page 110 of 698
REJ09B0146-0500