SH7706 Datasheet, PDF (66/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 2 CPU
• Status Register (SR)
The information of system status are set in this register.
Bit
Bit Name Initial Value R/W Description
31

0
R
Reserved
These bits always read as 0, and the write value
should always be 0.
30
MD
1
R/W Processor operation mode bit
Indicates the processor operation mode.
0: User mode
1: Privileged mode
MD is set to 1 when an exception or interruption
is occurred.
29
RB
1
R/W Register bank bit
Determines the bank of general registers R0 to
R7 used in privileged mode.
1: R0_BANK1 to R7_BANK1 and R8 to R15 are
general registers, and R0_BANK0 to
R7_BANK0 can be accessed by LDC/STC
instructions.
0: R0_BANK0 to R7_BANK0 and R8 to R15 are
general registers, and R0_BANK1 to
R7_BANK1 can be accessed by LDC/STC
instructions.
RB is set to 1 when an exception or interruption
is occurred.
28
BL
1
R/W Block bit
0: Exceptions and interrupts are accepted.
1: Exceptions and interrupts are suppressed.
See section 4, Exception Processing, for
details.
BL is set to 1 when an exception or interruption
is occurred.
27 to 13 
All 0
R
Reserved
These bits always read as 0, and the write value
should always be 0.
12
CL
0
R/W Cache lock bit
0: Cache look function is disabled.
1: Cache look function is enabled.
Rev. 5.00 May 29, 2006 page 18 of 698
REJ09B0146-0500