SH7706 Datasheet, PDF (47/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Table 16.4
Table 16.5
Table 16.6
Table 16.7
Table 16.8
Table 16.9
Maximum Bit Rates for Various Frequencies with Baud Rate Generator
(Asynchronous Mode)............................................................................................ 465
Maximum Bit Rates during External Clock Input (Asynchronous Mode) ............. 465
SCSMR2 Settings and SCIF Communication Formats .......................................... 469
SCSCR2 and SCSCR2 Settings and SCIF Clock Source Selection ....................... 470
Serial Communication Formats.............................................................................. 470
SCIF Interrupt Sources........................................................................................... 480
Section 17 Pin Function Controller (PFC)
Table 17.1 List of Multiplexed Pins ......................................................................................... 485
Section 18 I/O Ports
Table 18.1 Read/Write Operation of the Port A Data Register (PADR) .................................. 508
Table 18.2 Read/Write Operation of the Port B Data Register (PBDR) ................................. 510
Table 18.3 Read/Write Operation of the Port C Data Register (PCDR) .................................. 512
Table 18.4 Read/Write Operation of the Port D Data Register (PDDR) ................................. 514
Table 18.5 Read/Write Operation of the Port E Data Register (PEDR)................................... 516
Table 18.6 Read/Write Operation of the Port F Data Register (PFDR) ................................... 518
Table 18.7 Read/Write Operation of the Port G Data Register (PGDR) .................................. 520
Table 18.8 Read/Write Operation of the Port H Data Register (PHDR) .................................. 522
Table 18.9 Read/Write Operation of the Port J Data Register (PJDR)..................................... 524
Table 18.10 Read/Write Operation of the SC Port Data Register (SCPDR) .............................. 527
Section 19 A/D Converter (ADC)
Table 19.1 A/D Converter Pins ................................................................................................ 531
Table 19.2 Analog Input Channels and A/D Data Registers .................................................... 532
Table 19.3 A/D Conversion Time (Single Mode) .................................................................... 544
Table 19.4 Analog Input Pin Ratings ....................................................................................... 547
Table 19.5 Relationship between Access Size and Read Data ................................................. 548
Section 20 D/A Converter (DAC)
Table 20.1 D/A Converter Pins ................................................................................................ 550
Section 21 User Debugging Interface (H-UDI)
Table 21.1 Pin Configuraiton ................................................................................................... 554
Table 21.2 This LSI's Pins and Boundary Scan Register Bits .................................................. 556
Table 21.3 Reset Configuration................................................................................................ 562
Section 22 Power-Down Modes
Table 22.1 Power-Down Modes............................................................................................... 568
Table 22.2 Pin Configuration ................................................................................................... 569
Rev. 5.00 May 29, 2006 page xlvii of xlviii