SH7706 Datasheet, PDF (386/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 12 Timer Unit (TMU)
12.5.3 Interrupt Sources and Priorities
The TMU produces underflow interrupts for each channel. When the interrupt request flag and
interrupt enable bit are both set to 1, the interrupt is requested. Codes are set in the exception event
register (INTEVT, INTEVT2) for these interrupts and interrupt processing occurs according to the
codes.
The relative priorities of channels can be changed using the interrupt controller (see section 4,
Exception Processing, and section 6, Interrupt Controller (INTC)). Table 12.2 lists TMU interrupt
sources.
Table 12.2 TMU Interrupt Sources
Channel
0
1
2
Interrupt Source
TUNI0
TUNI1
TUNI2
TICPI2
Description
Priority
Underflow interrupt 0 High
Underflow interrupt 1
Underflow interrupt 2
Input capture interrupt 2 Low
12.6 Usage Note
12.6.1 Writing to Registers
Synchronization processing is not performed for timer counting during register writes. When
writing to registers, always clear the appropriate start bits for the channel (STR2 to STR0) in the
timer start register (TSTR) to halt timer counting.
12.6.2 Reading Registers
Synchronization processing is performed for timer counting during register reads. When timer
counting and register read processing are performed simultaneously, the register value before
TCNT counting down (with synchronization processing) is read.
Rev. 5.00 May 29, 2006 page 338 of 698
REJ09B0146-0500