SH7706 Datasheet, PDF(141/749 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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SH7706 Datasheet, PDF (141/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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Section 4 Exception Processing

â¢ Initial page write exception

ï£§ Conditions: A hit occurred to the TLB for a store access, but D = 0. (This occurs for initial

writes to the page registered by the load.)

ï£§ Operations: The virtual address (32 bits) that caused the exception is set in TEA and the

corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH

indicates the ASID at the time the exception occurred. The way that generated the

exception is set in the RC bit in MMUCR.

The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,

respectively. H'080 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a

branch occurs in PC = VBR + H'0100.

â¢ TLB protection exception

ï£§ Conditions: When a hit access violates the TLB protection information (PR bits) shown

below:

PR

Privileged mode

User mode

00

Only read enabled No access

01

Read/write enabled No access

10

Only read enabled Only read enabled

11

Read/write enabled Read/write enabled

ï£§ Operations: The virtual address (32 bits) that caused the exception is set in TEA and the

corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH

indicates the ASID at the time the exception occurred. The way that generated the

exception is set in the RC bits in MMUCR.

The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,

respectively. If the exception occurred during a read, H'0A0 is set in EXPEVT; if the exception

occurred during a write, H'0C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1

and a branch occurs to PC = VBR + H'0100.

â¢ Address error

ï£§ Conditions: When corresponded to the following items.

A. Instruction fetch from odd address (4n + 1, 4n + 3)

B. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)

C. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,

4n + 3)

D. Virtual space accessed in user mode in the area H'80000000 to H'FFFFFFFF.

Rev. 5.00 May 29, 2006 page 93 of 698

REJ09B0146-0500

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