SH7706 Datasheet, PDF (376/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 12 Timer Unit (TMU)
12.3.3 Timer Control Registers 0 to 2 (TCR_0 to TCR_2)
The timer control registers (TCR_0 to TCR_2) control the timer counters (TCNT_0 to TCNT_2)
and interrupts. The TMU has three TCR_0 to TCR_2 registers for each channel.
The TCR_0 to TCR_2R registers are 16-bit read/write registers that control the issuance of
interrupts when the flag indicating timer counter (TCNT_0 to TCNT_2) underflow has been set to
1, and also carry out counter clock selection. When the external clock has been selected, they also
select its edge. Additionally, TCR_2 controls the channel 2 input capture function and the issuance
of interrupts during input capture. The TCR_0 to TCR_2 are initialized to H'0000 by a power-on
reset and manual reset. They are not initialized in standby mode.
In cases of Channel 0 and 1:
Bit
Bit Name Initial Value R/W
15 to 9 —
All 0
R
8
UNF
0
R/W
7, 6 —
All 0
R
5
UNIE
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Underflow Flag
Status flag that indicates occurrence of a TCNT_0
and TCNT_1 underflow.
0: TCNT has not underflowed.
[Clearing condition]
When 0 is written to UNF
1: TCNT has underflowed.
[Setting condition]
When TCNT_0 and TCNT_1 underflows*
Note: * Contents do not change when 1 is written to
UNF.
Reserved
These bits are always read as 0. The write value
should always be 0.
Underflow Interrupt Control
Controls enabling of interrupt generation when the
status flag (UNF) indicating TCNT_0 and TCNT_1
underflow has been set to 1.
0: Interrupt due to UNF (TUNI) is not enabled.
1: Interrupt due to UNF (TUNI) is enabled.
Rev. 5.00 May 29, 2006 page 328 of 698
REJ09B0146-0500