SH7706 Datasheet, PDF (446/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
1
Serial
data
Start
bit
0 D0
Data
Parity Stop Start
bit bit bit
D1
D ₇ 0/1 1 0 D ₀
Data
Parity
bit
D1
D ₇ 0/1
Stop
bit
1
1
Idling
(marking)
TDRE
TEND
TXI interrupt
request
generated
Writes data to
SCTDR with the
TXI interrupt
processing routine
and clear TDRE
bit to 0
TXI interrupt
request
generated
TEI interrupt
request
generated
1 frame
Example: 8-bit data with parity and one stop bit
Figure 14.9 SCI Transmit Operation in Asynchronous Mode
Rev. 5.00 May 29, 2006 page 398 of 698
REJ09B0146-0500