SH7706 Datasheet, PDF (630/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 22 Power-Down Modes
22.3.5 Hardware Standby Function
Transition to Hardware Standby Mode
Driving the CA pin low causes a transition to hardware standby mode. In hardware standby mode,
all modules except those operating on an RTC clock are halted, as in the software standby mode
entered on execution of a SLEEP instruction ((software) standby mode).
Hardware standby mode differs from software standby mode as follows.
1. Interrupts and manual resets are not accepted.
2. The TMU does not operate.
Operation when a low-level signal is input at the CA pin depends on the CPG state, as follows.
1. In software standby mode
The clock remains stopped and the chip enters the hardware standby state. Acceptance of
interrupts and manual resets is disabled, TCLK output is fixed low, and the TMU halts.
2. During WDT operation when software standby mode is canceled by an interrupt
The chip enters hardware standby mode after standby mode is canceled and the CPU resumes
operation.
3. In sleep mode
The chip enters hardware standby mode after sleep mode is canceled and the CPU resumes
operation.
Hold the CA pin low in hardware standby mode.
In hardware standby mode, the LSI can supply power only to the RTC power-supply pin.
Canceling Hardware Standby Mode
Hardware standby mode can only be canceled by a power-on reset.
When the CA pin is driven high while the RESETP pin is low, clock oscillation is started. Hold
the RESETP pin low until clock oscillation stabilizes. When the RESETP pin is driven high, the
CPU begins power-on reset processing.
If an interrupt or manual reset is input, correct operation cannot be guaranteed.
Rev. 5.00 May 29, 2006 page 582 of 698
REJ09B0146-0500