SH7706 Datasheet, PDF (191/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 7 User Break Controller
Bit
Bit Name
15 to 8 —
Initial Value R/W
All 0
R
7
CDA1
0
R/W
6
CDA0
0
R/W
5
IDA1
0
R/W
4
IDA0
0
R/W
3
RWA1
0
R/W
2
RWA0
0
R/W
1
SZA1
0
R/W
0
SZA0
0
R/W
Legend: X: Don't care
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
CPU Cycle/DMAC Cycle Select A
Selects the CPU cycle or DMAC cycle as the bus
cycle of the channel A break condition.
00: Condition comparison is not performed
X1: The break condition is the CPU cycle
10: The break condition is the DMAC cycle
Instruction Fetch/Data Access Select A
Selects the instruction fetch cycle or data access
cycle as the bus cycle of the channel A break
condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch
cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch
cycle or data access cycle
Read/Write Select A
Selects the read cycle or write cycle as the bus
cycle of the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write
cycle
Operand Size Select A
Selects the operand size of the bus cycle for the
channel A break condition.
00: The break condition does not include
operand size
11: The break condition is byte access
10: The break condition is word access
11: The break condition is longword access
Rev. 5.00 May 29, 2006 page 143 of 698
REJ09B0146-0500