SH7706 Datasheet, PDF (200/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 7 User Break Controller
7.2.12 Branch Destination Register (BRDR)
BRDR is a 32-bit read register. BRDR stores the branch destination fetch address. BRDR has the
flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRDR is read and
also initialized by power-on resets or manual resets. Other bits are not initialized by resets. Eight
BRDR registers have queue structure and a stored register is shifted every branch.
Bit
Bit Name Initial Value
31
DVF
0
30 to 28 —
—
27 to 0 BDA27 to —
BDA0
R/W Description
R BRDR Valid Flag
Indicates whether a branch destination address is
stored. When a branch destination address is
fetched, this flag is set to 1. This flag is set to 0 in
reading BRDR.
0: The value of BRDR register is invalid
1: The value of BRDR register is valid
R Reserved
These bits are always read as 0. The write value
should always be 0.
R Branch Destination Address
These bits store the first fetched address after
branch.
7.2.13 Break ASID Register A (BASRA)
Break ASID register A (BASRA) is an 8-bit read/write register that specifies the ASID that serves
as the break condition for channel A. It is not initialized by resets. It is located in CCN.
Bit
7 to 0
Bit Name Initial Value
BASA7 to —
BASA0
R/W Description
R/W Break ASID
These bits store the ASID (bits 7 to 0) that is the
channel A break condition.
Rev. 5.00 May 29, 2006 page 152 of 698
REJ09B0146-0500