SH7706 Datasheet, PDF (123/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 3 Memory Management Unit (MMU)
3.5.5
Processing Flow in Event of MMU Exception (Same Processing Flow for CPU
Address Error)
Figure 3.11 shows the MMU exception signals in the instruction fetch mode.
IF ID EX MA WB
ID EX MA
ID EX
MMU exception handler
WB
MA
NOP
IF
WB
NOP
ID
Handler transition
processing
EX MA WB
: Exception source stage
Legend:
IF = Instruction fetch
ID = Instruction decode
EX = Instruction execution
MA = Memory access
WB = Write back
NOP = No operation
Figure 3.11 MMU Exception Signals in Instruction Fetch
Rev. 5.00 May 29, 2006 page 75 of 698
REJ09B0146-0500