SH7706 Datasheet, PDF (243/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Bit
Bit Name Initial Value R/W Description
2
OVF
0
R/W Refresh Count Overflow Flag
The OVF status flag indicates when the number of
refresh requests indicated in the refresh count
register (RFCR) exceeds the limit set in the LMTS
bit of RTCSR.
0: RFCR has not exceeded the count limit value
set in LMTS
Clear Conditions: When 0 is written to OVF
1: RFCR has exceeded the count limit value set in
LMTS
Set Conditions: When the RFCR value has
exceeded the count limit value set in LMTS*
Note: * Contents don't change when 1 is written to
OVF.
1
OVIE
0
R/W Refresh Count Overflow Interrupt Enable
OVIE selects whether to suppress generation of
interrupt requests by OVF when the OVF bit of
RTCSR is set to 1.
0: Disables interrupt requests from the OVF
1: Enables interrupt requests from the OVF
0
LMTS
0
R/W Refresh Count Overflow Limit Select
Indicates the count limit value to be compared to
the number of refreshes indicated in the refresh
count register (RFCR). When the value RFCR
overflows the value specified by LMTS, the OVF
flag is set.
0: Count limit value is 1024
1: Count limit value is 512
Rev. 5.00 May 29, 2006 page 195 of 698
REJ09B0146-0500