SH7706 Datasheet, PDF (103/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 3 Memory Management Unit (MMU)
Physical Address Space: This LSI supports a 32-bit physical address space, but the upper 3 bits
are actually ignored and treated as a shadow. See section 8, Bus State Controller (BSC), for
details.
Address Translation: When the MMU is enabled, the virtual address space is divided into units
called pages. Physical addresses are translated in page units. Address translation tables in external
memory hold information such as the physical address that corresponds to the virtual address and
memory protection codes. When an access to areas P1 or P2 occurs, there is no TLB access and
the physical address is defined uniquely by hardware. If it belongs to area P0, P3 or U0, the TLB
is searched by virtual address and, if that virtual address is registered in the TLB, the access hits
the TLB. The corresponding physical address and the page control information are read from the
TLB and the physical address is determined.
If the virtual address is not registered in the TLB, a TLB miss exception occurs and processing
will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in
external memory is searched and the corresponding physical address and the page control
information are registered in the TLB. After returning from the handler, the instruction that caused
the TLB miss is re-executed. When the MMU is enabled, address translation information that
results in a physical address space of H'80000000 to H'FFFFFFFF should not be registered in the
TLB.
When the MMU is disabled, the virtual address is used directly as the physical address. As this
LSI supports a 29-bit address space as the physical address space, the top 3 bits of the physical
address are ignored, and constitute a shadow space. For example, addresses H'00001000 in the P0
area, H'80001000 in the P1 area, H'A0001000 in the P2 area, and H'C0001000 in the P3 area are
all mapped onto the same physical address. When access to these addresses is performed with the
cache enabled, an address with the top 3 bits of the physical address masked to 0 is stored in the
cache address array to ensure data congruity.
Single Virtual Memory Mode and Multiple Virtual Memory Mode: There are two virtual
memory modes: single virtual memory mode and multiple virtual memory mode. In single virtual
memory mode, multiple processes run in parallel using the virtual address space exclusively and
the physical address corresponding to a given virtual address is specified uniquely. In multiple
virtual memory mode, multiple processes run in parallel sharing the virtual address space, so a
given virtual address may be translated into different physical addresses depending on the process.
By the value set to the MMU control register (MMUCR), either single or multiple virtual mode is
selected.
In terms of operation, the only difference between single virtual memory mode and multiple
virtual memory mode is the TLB address comparison method.
Rev. 5.00 May 29, 2006 page 55 of 698
REJ09B0146-0500