SH7706 Datasheet, PDF (610/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 21 User Debugging Interface (H-UDI)
21.4.2 Reset Configuration
Table 21.3 Reset Configuration
ASDMD0^*1
RESETP
TRST
Chip State
H
L
L
Normal reset and H-UDI reset
H
Normal reset
H
L
H-UDI reset only
H
Normal operation
L
L
L
Reset hold^*2
H
During ASE user mode^*3: Normal reset
During ASE break mode^*3: RESETP assert is
masked
H
L
H-UDI reset only
H
Normal operation
Notes: 1. Performs normal operation mode and ASE mode settings
ASEMD0 = H, normal operation mode
ASEMD0 = L, ASE mode
ASEMD0 pin should be high level when an emulator or H-UDI is not used.
2. During ASE mode, reset hold is enabled by setting RESETP and TRST pins at low level
for a constant cycle. In this state, the CPU does not start up, even if RESETP is set to
high level. When TRST is set to high level, H-UDI operation is enabled, but the CPU
does not start up. The reset hold state is cancelled by the following:
• Boot request from H-UDI (boot sequence)
• Another RESETP assert (power-on reset)
3. ASE mode can be divided by two modes: a mode to execute the firmware program of
the emulator (ASE break mode) and a mode to execute the user program (ASE user
mode).
Rev. 5.00 May 29, 2006 page 562 of 698
REJ09B0146-0500