SH7706 Datasheet, PDF (585/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 19 A/D Converter (ADC)
Figure 19.2 shows the data flow for access to an A/D data register.
Upper byte read
CPU
(H'AA)
Bus
interface
Module internal data bus
TEMP
(H'40)
Lower byte read
CPU
(H'40)
Upper byte of
A/D data register
(H'AA)
Lower byte of
A/D data register
(H'40)
Bus
interface
Module internal data bus
TEMP
(H'40)
Upper byte of
A/D data register
(H'AA)
Lower byte of
A/D data register
(H'40)
Figure 19.2 A/D Data Register Access Operation (Reading H'AA40)
Rev. 5.00 May 29, 2006 page 537 of 698
REJ09B0146-0500