SH7706 Datasheet, PDF (201/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 7 User Break Controller
7.2.14 Break ASID Register B (BASRB)
Break ASID register B (BASRB) is an 8-bit read/write register that specifies the ASID that serves
as the break condition for channel B. It is not initialized by resets. It is located in CCN.
Bit
7 to 0
Bit Name
BASB7 to
BASB0
Initial Value R/W
—
R/W
Description
Break ASID
These bits store the ASID (bits 7 to 0) that is the
channel B break condition.
7.3 Operation
7.3.1 Flow of the User Break Operation
The flow from setting of break conditions to user break exception processing is described below:
1. The break addresses and the corresponding ASIDs are loaded in the BARA, BARB, BASRA
and BASRB. The masked addresses are set in the BAMRA and BAMRB. The break data is set
in the BDRB. The masked data is set in the BDMRB. The breaking bus conditions are set in
the BBRA and BBRB. Three groups of the BBRA and BBRB (CPU cycle/DMAC cycle select,
instruction fetch/data access select, and read/write select) are each set. No user break will be
generated if even one of these groups is set with 00. The respective conditions are set in the
bits of the BRCR.
2. When the break conditions are satisfied, the UBC sends a user break request to the interrupt
controller. The break type will be sent to CPU indicating the instruction fetch, pre/post
instruction break, or data access break. When conditions match up, the CPU condition match
flags (SCMFCA and SCMFCB) and DMAC condition match flags (SCMFDA and SCMFDB)
for the respective channels are set.
3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can
be used to check if the set conditions match or not. The matching of the conditions sets flags,
but they are not reset. 0 must first be written to them before they can be used again.
4. There is a chance that the data access break and its following instruction fetch break occur
around the same time, there will be only one break request to the CPU, but these two break
channel match flags could be both set.
Rev. 5.00 May 29, 2006 page 153 of 698
REJ09B0146-0500