SH7706 Datasheet, PDF (591/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 19 A/D Converter (ADC)
ADST
ADF
Channel 0 (AN₀)
operating
Channel 1 (AN₁)
operating
Channel 2 (AN₂)
operating
Channel 3 (AN₃)
operating
ADDRA^*2
ADDRB^*2
ADDRC^*2
Set^*1
Continuous A/D conversion
Clear^*1
Clear^*1
Waiting
Waiting
Waiting
Waiting
A/D conversion 1
Waiting
A/D conversion 2
A/D conversion 4
Waiting
A/D conversion 5
A/D conversion 3
Waiting
Waiting
Waiting
Transfer
A/D conversion result 1
A/D conversion result 4
A/D conversion result 2
A/D conversion result 3
ADDRD^*2
Notes: 1. Downward arrows indicate instruction executed by software.
2. Data is ignored during conversion.
Figure 19.7 Example of A/D Converter Operation (Scan Mode,
Channels AN0 to AN2 Selected)
19.6.4 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t_D after the ADST bit in ADCSR is set to 1, then starts conversion. Figure 19.8
shows the A/D conversion timing. Table 19.3 indicates the A/D conversion time.
As indicated in figure 19.8, the A/D conversion time includes t_D and the input sampling time. The
length of t_D varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 19.3.
In multi mode and scan mode, the values given in table 19.3 apply to the first conversion. In the
second and subsequent conversions the conversion time is fixed at 512 states when CKS = 0 or
256 states when CKS = 1.
Rev. 5.00 May 29, 2006 page 543 of 698
REJ09B0146-0500