SH7706 Datasheet, PDF (45/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Table 6.7 Interrupt Response Time ........................................................................................ 136
Section 7 User Break Controller
Table 7.1 Data Access Cycle Addresses and Operand Size Comparison Conditions ............ 154
Section 8 Bus State Controller (BSC)
Table 8.1 Pin Configuration ................................................................................................... 165
Table 8.2 Physical Address Space Map ................................................................................. 168
Table 8.3 Correspondence between External Pins (MD4 and MD3) and Memory Size ........ 169
Table 8.4 PCMCIA Interface Characteristics......................................................................... 170
Table 8.5 PCMCIA Support Interface.................................................................................... 171
Table 8.6 Area 6 Wait Control (Normal Memory I/F) ........................................................... 184
Table 8.7 Area 5 Wait Control (Normal Memory I/F) ........................................................... 184
Table 8.8 Area 4 Wait Control ............................................................................................... 185
Table 8.9 Area 0 Wait Control ............................................................................................... 185
Table 8.10 Area 6 Wait Control (PCMCIA I/F)....................................................................... 192
Table 8.11 32-Bit External Device/Big Endian Access and Data Alignment .......................... 198
Table 8.12 16-Bit External Device/Big Endian Access and Data Alignment .......................... 198
Table 8.13 8-Bit External Device/Big Endian Access and Data Alignment ............................ 199
Table 8.14 32-Bit External Device/Little Endian Access and Data Alignment ....................... 200
Table 8.15 16-Bit External Device/Little Endian Access and Data Alignment ....................... 200
Table 8.16 8-Bit External Device/Little Endian Access and Data Alignment ......................... 201
Table 8.17 Relationship between Bus Width, AMX, and Address Multiplex Output.............. 214
Table 8.18 Example of Correspondence between this LSI and Synchronous DRAM
Address Pins (AMX (3 to 0) = 0100 (32-Bit Bus Width)) ..................................... 215
Section 9 Direct Memory Access Controller (DMAC)
Table 9.1 Pin Configuration ................................................................................................... 254
Table 9.2 Selecting External Request Modes with the RS Bits.............................................. 267
Table 9.3 Selecting On-Chip Peripheral Module Request Modes with the RS Bit ................ 268
Table 9.4 Supported DMA Transfers ..................................................................................... 272
Table 9.5 Relationship of Request Modes and Bus Modes by DMA Transfer Category....... 283
Table 9.6 Transfer Conditions and Register Settings for Transfer between On-Chip A/D
Converter and External Memory ............................................................................ 298
Table 9.7 Values in the DMAC after the Fourth Transfer Ends............................................. 299
Table 9.8 Transfer Conditions and Register Settings for Transfer between External
Memory and SCIF Transmitter .............................................................................. 300
Section 10 Clock Pulse Generator (CPG)
Table 10.1 Clock Pulse Generator Pins and Functions............................................................. 306
Table 10.2 Clock Operating Modes.......................................................................................... 307
Rev. 5.00 May 29, 2006 page xlv of xlviii