SH7706 Datasheet, PDF (478/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 15 Smart Card Interface
2. Setting the bit rate register (SCBRR): Set the bit rate. See section 15.4.5, Clock, to see how to
calculate the set value.
3. Setting the serial control register (SCSCR): The TIE, RIE, TE and RE bits function as they do
for the ordinary SCI. See section 14, Serial Communication Interface (SCI), for more
information. The CKE0 bit specifies the clock output. When no clock is output, set 0; when a
clock is output, set 1.
4. Setting the smart card mode register (SCSCMR): The SDIR and SINV bits are both set to 0 for
IC cards that use the direct convention and both to 1 when the inverse convention is used. The
SMIF bit is set to 1 for the smart card interface.
Figure 15.4 shows sample waveforms for register settings of the two types of IC cards (direct
convention and inverse convention) and their start characters.
In the direct convention type, the logical 1 level is state Z, the logical 0 level is state A, and
communication is LSB first. The start character data is H'3B. The parity bit is even (as specified in
the smart card standards), and thus 1.
In the inverse convention type, the logical 1 level is state A, the logical 0 level is state Z, and
communication is MSB first. The start character data is H'3F. The parity bit is even (as specified
in the smart card standards), and thus 0, which corresponds to state Z.
Only data bits D7 to D0 are inverted by the SINV bit. To invert the parity bit, set the O/E bit in
SCSMR to odd parity mode. This applies to both transmission and reception.
(Z) A Z Z A Z Z Z A A Z (Z) State
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
a. Direct convention (SDIR, SINV, and O/E are all 0)
(Z) A Z Z A A A A A A Z (Z) State
Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp
b. Inverse convention (SDIR, SINV, and O/E are all 1)
Figure 15.4 Waveform of Start Character
Rev. 5.00 May 29, 2006 page 430 of 698
REJ09B0146-0500