SH7706 Datasheet, PDF (580/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 19 A/D Converter (ADC)
19.3.1 A/D Data Registers A to D (ADDRA to ADDRD)
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte (bits 15 to 8) of the A/D data register. The lower 2 bits are stored in the lower byte (bits 7 and
6). Bits 5 to 0 of an A/D data register are reserved bits that always read 0. For the reading of the
data, see section 19.4, Bus Master Interface, and section 19.9.3, Access Size and Read Data. Table
19.2 indicates the pairings of analog input channels and A/D data registers.
Bit
15 to 6
5 to 0
Bit Name Initial Value R/W
AD9 to AD0 All 0
R

All 0
R
Description
Bit data (10 bits)
Reserved
These bits are always read as 0.
Table 19.2 Analog Input Channels and A/D Data Registers
Analog Input Channel
Group 0
AN0
AN1
AN2
AN3
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
Rev. 5.00 May 29, 2006 page 532 of 698
REJ09B0146-0500