SH7706 Datasheet, PDF (41/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Figure 19.8
Figure 19.9
Figure 19.10
Figure 19.11
Figure 19.12
A/D Conversion Timing ...................................................................................... 544
External Trigger Input Timing............................................................................. 545
Definitions of A/D Conversion Accuracy............................................................ 546
Example of Analog Input Protection Circuit ....................................................... 547
Analog Input Pin Equivalent Circuit.................................................................... 547
Section 20 D/A Converter (DAC)
Figure 20.1 D/A Converter Block Diagram ............................................................................ 549
Figure 20.2 Example of D/A Converter Operation ................................................................. 552
Section 21 User Debugging Interface (H-UDI)
Figure 21.1 H-UDI Block Diagram......................................................................................... 553
Figure 21.2 TAP Controller State Transitions......................................................................... 561
Figure 21.3 H-UDI Reset ........................................................................................................ 563
Section 22 Power-Down Modes
Figure 22.1 Canceling Software Standby Mode with STBCR.STBY..................................... 575
Figure 22.2 Power-On Reset STATUS Output ....................................................................... 578
Figure 22.3 Manual Reset STATUS Output ........................................................................... 578
Figure 22.4 Software Standby to Interrupt STATUS Output .................................................. 579
Figure 22.5 Software Standby to Power-On Reset STATUS Output...................................... 579
Figure 22.6 Software Standby to Manual Reset STATUS Output .......................................... 580
Figure 22.7 Sleep to Interrupt STATUS Output ..................................................................... 580
Figure 22.8 Sleep to Power-On Reset STATUS Output ......................................................... 581
Figure 22.9 Sleep to Manual Reset STATUS Output ............................................................. 581
Figure 22.10 Hardware Standby Mode (When CA Goes Low in Normal Operation) .............. 583
Figure 22.11 Hardware Standby Mode Timing (When CA Goes Low during WDT
Operation on Standby Mode Cancellation).......................................................... 584
Section 24 Electrical Characteristics
Power-On Sequence..................................................................................................................... 608
Figure 24.1 EXTAL Clock Input Timing................................................................................ 614
Figure 24.2 CKIO Clock Input Timing ................................................................................... 614
Figure 24.3 CKIO Clock Output Timing ................................................................................ 614
Figure 24.4 Power-On Oscillation Settling Time.................................................................... 615
Figure 24.5 Oscillation Settling Time at Standby Return (Return by Reset) .......................... 615
Figure 24.6 Oscillation Settling Time at Standby Return (Return by NMI) ........................... 616
Figure 24.7 Oscillation Settling Time at Standby Return (Return by IRQ or IRL)................. 616
Figure 24.8 PLL Synchronization Settling Time by Reset or NMI at the Returning
from Standby Mode (Return by Reset or NMI) ................................................... 617
Rev. 5.00 May 29, 2006 page xli of xlviii