SH7706 Datasheet, PDF (241/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
8.4.7 Synchronous DRAM Mode Register (SDMR)
The synchronous DRAM mode register (SDMR) is written to via the synchronous DRAM address
bus and is an 8-bit write-only register. It sets synchronous DRAM mode for areas 2 and 3. SDMR
must be set before synchronous DRAM is accessed.
Writes to the synchronous DRAM mode register use the address bus rather than the data bus. If the
value to be set is X and the SDMR address is Y, the value X is written in the synchronous DRAM
mode register by writing in address X + Y. Since, with a 32-bit bus width, A0 of the synchronous
DRAM is connected to A2 of the chip and A1 of the synchronous DRAM is connected to A3 of
the chip, the value actually written to the synchronous DRAM is the X value shifted two bits right.
With a 16-bit bus width, the value written is the X value shifted one bit right. For example, with a
32-bit bus width, when H'0230 is written to the SDMR register of area 2, random data is written to
the address H'FFFFD000 (address Y) + H'08C0 (value X), or H'FFFFD8C0. As a result, H'0230 is
written to the SDMR register. The range for value X is H’0000 to H'0FFC. When H'0230 is
written to the SDMR register of area 3, random data is written to the address H'FFFFE000
(address Y) + H'08C0 (value X), or H'FFFFE8C0. As a result, H'0230 is written to the SDMR
register. The range for value X is H'0000 to H'0FFC.
8.4.8 Refresh Timer Control/Status Register (RTCSR)
The refresh timer control/status register (RTCSR) is a 16-bit read/write register that specifies the
refresh cycle, whether to generate an interrupt, and that interrupt's cycle. It is initialized to H'0000
by a power-on reset, but is not initialized by a manual reset or standby mode and holds its values
unchanged. Make the RTCOR setting before setting bits CKS2 to CKS0 in RTCSR.
Note:
Writing to the RTCSR differs from that to general registers to ensure the RTCSR is not
rewritten incorrectly. Use the word-transfer instruction to set the upper byte as
B'10100101 and the lower byte as the write data. For the byte-transfer instruction, writing
is disabled. Read data in 16 bits. 0 is read from undefined bits.
Rev. 5.00 May 29, 2006 page 193 of 698
REJ09B0146-0500