SH7706 Datasheet, PDF (326/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
CK
A25 to A0
CSn
Transfer source
address (H)
Transfer source
address (L)
NOP
Indirect address
NOP
Transfer destination
address
D31 to D0
Internal
addresu bus
Internal
data bus
DMAC indirect
address buffer
DMAC data
buffer
Indirect
address(H)
Transfer source
address*¹
Indirect
address(L)
NOP
Transfer source address*²
Indirect
address
Transfer
data
Transfer
data
Transfer
data
Transfer
data
Indirect address
Transfer
data
RD
WEn
Address read cycle
(1st)
(2nd)
NOP
cycle
Data
read cycle
(3rd)
NOP
cycle
Data
write cycle
(4th)
Notes: 1. The internal address bus value does not change, and controlled by the port.
2. The DMAC does not fetch the value until 32-bit data is output to the internal data bus.
Figure 9.10 Example of Transfer Timing in the Indirect Address Mode
in the Dual Address Mode
Rev. 5.00 May 29, 2006 page 278 of 698
REJ09B0146-0500