SH7706 Datasheet, PDF (335/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
CKIO
1st sampling
DREQ
DRAK
(High active)
Bus cycle
DACK
(RD output)
CPU
2nd sampling is performed,
but since DREQ is high,
per-cycle sampling starts
2nd sampling
DMAC(Read)
DMAC(Write)
3rd sampling is performed,
but since DREQ is high,
per-cycle sampling starts
3rd sampling
CPU
DMAC(Read)
DMAC(Write)
CPU
Figure 9.20 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed)
CKIO
1st sampling
2nd sampling is performed,
but since there is no DREQ falling edge,
per-cycle sampling starts
2nd sampling
3rd sampling is performed,
but since there is no DREQ falling edge,
per-cycle sampling starts
3rd sampling
DREQ
DRAK
(High active)
Bus cycle
DACK
(RD output)
CPU
High High
DMAC(Read)
DMAC(Write)
CPU
High High
DMAC(Read)
DMAC(Write)
CPU
Note: When a DREQ falling edge is detected, DREQ must be high for at least one cycle before the sampling point.
Figure 9.21 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles)
1st sampling
CKIO
DREQ
DRAK
(High active)
Bus cycle
DACK
CPU
2nd sampling
3rd sampling
DMAC(Read)
DMAC(Write)
DMAC(Read)
DMAC(Write)
Figure 9.22 Burst Mode, Level Input
DMAC(Read)
Rev. 5.00 May 29, 2006 page 287 of 698
REJ09B0146-0500