SH7706 Datasheet, PDF (401/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 13 Realtime Clock (RTC)
Bit Bit Name Initial Value R/W Description
3
AIE
0
R/W Alarm Interrupt Enable Flag
When the alarm flag (AF) is set to 1, the AIE bit allows
interrupts.
0: An alarm interrupt is not generated when the AF flag
is set to 1
1: An alarm interrupt is generated when the AF flag is
set to 1
2, 1 —
All 0
R Reserved
These bits are always read as 0. The write value
should always be 0.
0
AF
0
R/W Alarm Flag
The AF flag is set to 1 when the alarm time set in an
alarm register (only registers with ENB bit set to 1)
matches the clock and calendar time. This flag is
cleared to 0 when 0 is written, but holds the previous
value when 1 is to be written.
0: Clock/calendar and alarm register have not matched
since last reset to 0.
[Clearing condition]
When 0 is written to AF
1: [Setting condition]
Clock/calendar and alarm register have matched
(only registers that ENB bit is 1)
Rev. 5.00 May 29, 2006 page 353 of 698
REJ09B0146-0500