SH7706 Datasheet, PDF (726/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Appendix
B.4
Pin States in Access to Each Address Space
Table B.3 Pin States (Normal Memory/Little Endian)
Pin
CS6 to CS2, CS0
RD
RD/WR
BS
RASU/PTD[1]
RASL/PTD[0]
CASL/PTD[2]
CASU/PTD[3]
WE0/DQMLL
WE1/WE/DQMLU
WE2/ICIORD/DQMUL/
PTC[1]
WE3/ICIOWR/DQMUU/
PTC[2]
CE2A/PTD[6]
CE2B/PTD[7]
CKE
WAIT
IOIS16
A25 to A0
D7 to D0
D15 to D8
D31 to D16
8-Bit Bus Width
Byte/Word/
Longword Access
Enabled
R Low
W High
R High
W Low
Enabled
High
High
High
High
R High
W Low
R High
W High
R High
W High
R High
W High
High
High
Disabled
Enabled^*1
Disabled
Address
Valid data
Hi-Z^*2
Hi-Z^*2
Byte Access
(Address 2n)
Enabled
Low
High
High
Low
Enabled
High
High
High
High
High
Low
High
High
High
High
High
High
High
High
Disabled
Enabled^*1
Disabled
Address
Valid data
Invalid data
Hi-Z^*2
16-Bit Bus Width
Byte Access
(Address 2n + 1)
Enabled
Low
High
High
Low
Enabled
High
High
High
High
High
High
High
Low
High
High
High
High
High
High
Disabled
Enabled^*1
Disabled
Address
Invalid data
Valid data
Hi-Z^*2
Word/Longword
Access
Enabled
Low
High
High
Low
Enabled
High
High
High
High
High
Low
High
Low
High
High
High
High
High
High
Disabled
Enabled^*1
Disabled
Address
Valid data
Valid data
Hi-Z^*2
Rev. 5.00 May 29, 2006 page 678 of 698
REJ09B0146-0500