SH7706 Datasheet, PDF (328/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
Figures 9.12 to 9.14 show examples of DMA transfer timing in the single address mode.
CKI0
A25 to A0
CSn
WE
D31 to D0
DACKn
BS
Address output to external memory space
Write strobe signal to external memory space
Data output from external device with DACK
DACK signal (active-low) to external device with DACK
(a) External device with DACK → external memory space (ordinary memory)
CKI0
A25 to A0
CSn
RD
Address output to external memory space
Read strobe signal to external memory space
D31 to D0
DACKn
BS
Data output from external memory space
DACK signal (active-low) to external device with DACK
(b) External memory space → external device with DACK (active low)
Figure 9.12 Example of DMA Transfer Timing in the Single Address Mode
Rev. 5.00 May 29, 2006 page 280 of 698
REJ09B0146-0500