SH7706 Datasheet, PDF (425/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
Bit Bit Name Initial Value R/W Description
5 ORER
0
R/(W)* Overrun Error
Indicates that data reception aborted due to an
overrun error.
0: Receiving is in progress or has ended normally^*1
[Clearing conditions]
1. The chip is reset or enters standby mode.
2. ORER is read as 1, then written to with 0.
1: A receive overrun error occurred^*2
[Setting condition]
Reception of the next serial data has ended when
RDRF is set to 1.
Notes: 1. Clearing the RE bit to 0 in the serial control
register does not affect the ORER bit, which
retains its previous value.
2. SCRDR continues to hold the data received
before the overrun error, so subsequent
receive data is lost. Serial receiving cannot
continue while ORER is set to 1. In the clock
synchronous mode, serial transmitting is
also disabled.
Rev. 5.00 May 29, 2006 page 377 of 698
REJ09B0146-0500