SH7706 Datasheet, PDF (189/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 7 User Break Controller
7.2 Register Description
The UBC has the following registers. Refer to section 23, List of Registers, for more details of the
addresses and access sizes.
• Break address register A (BARA)
• Break address mask register A (BAMRA)
• Break bus cycle register A (BBRA)
• Break address register B (BARB)
• Break address mask register B (BAMRB)
• Break bus cycle register B (BBRB)
• Break data register B (BDRB)
• Break data mask register B (BDMRB)
• Break control register (BRCR)
• Execution count break register (BETR)
• Branch source register (BRSR)
• Branch destination register (BRDR)
• Break ASID register A (BASRA)
• Break ASID register B (BASRB)
7.2.1 Break Address Register A (BARA)
BARA is a 32-bit read/write register. BARA specifies the address used as a break condition in
channel A.
Bit
31 to 0
Bit Name
BAA31 to
BAA0
Initial Value R/W
All 0
R/W
Description
Break Address
Stores the address on the LAB or IAB that
specifies break conditions of channel A.
Rev. 5.00 May 29, 2006 page 141 of 698
REJ09B0146-0500