SH7706 Datasheet, PDF (257/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2
settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a
software wait is inserted in accordance with that specification. For details, see section 8.4.4, Wait
State Control Register 2 (WCR2)
The specified number of Tw cycles are inserted as wait cycles using the basic interface wait timing
shown in figure 8.9.
T1
Tw
T2
CKIO
A25 to A0
CSn
Read
Write
RD/WR
RD
D31 to D0
WEn
D31 to D0
BS
Figure 8.9 Basic Interface Wait Timing (Software Wait Only)
When software wait insertion is specified by WCR2, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 8.10. A 2-cycle wait is specified as a software
wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore, if the
WAIT signal has no effect if asserted in the T1 cycle or the first Tw cycle.
When the WAITSEL bit in the WCR1 register is set to 1, the WAIT signal is sampled at the
falling edge of the clock. If the setup time and hold times with respect to the falling edge of the
clock are not satisfied, the value sampled at the next falling edge is used.
Rev. 5.00 May 29, 2006 page 209 of 698
REJ09B0146-0500