SH7706 Datasheet, PDF (217/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Area 0: H'00000000
Area 1: H'04000000
Area 2: H'08000000
Area 3: H'0C000000
Area 4: H'10000000
Area 5: H'14000000
Area 6: H'18000000
Ordinary memory/
burst ROM
Internal I/O
Ordinary memory/
synchronous DRAM
Ordinary memory/
synchronous DRAM
Ordinary memory
Ordinary memory/
burst ROM/PCMCIA
Ordinary memory/
burst ROM/PCMCIA
The PCMCIA interface is shared
by the memory and I/O card
The PCMCIA interface is shared
by the memory and I/O card
Figure 8.3 Physical Space Allocation
Memory Bus Width: The memory bus width in this LSI can be set for each area. In area 0, an
external pin can be used to select byte (8 bits), word (16 bits), or longword (32 bits) on power-on
reset. The correspondence between the external pins (MD4 and MD3) and memory size is listed in
table below.
Table 8.3 Correspondence between External Pins (MD4 and MD3) and Memory Size
MD4
0
0
1
1
MD3
0
1
0
1
Memory Size
Reserved (Setting prohibited)
8 bits
16 bits
32 bits
For areas 2 to 6, byte, word, and longword may be chosen for the bus width using bus control
register 2 (BCR2) whenever ordinary memory, ROM, or burst ROM are used. When the
synchronous DRAM interface is used, word or longword can be chosen as the bus width.
When the PCMCIA interface is used, set the bus width to byte or word. When synchronous
DRAM is connected to both area 2 and area 3, set the same bus width for areas 2 and 3. When
using port A or B, set a bus width of 8 or 16 bits for all areas. For more information, see section
8.4.2, Bus Control Register 2 (BCR2).
Rev. 5.00 May 29, 2006 page 169 of 698
REJ09B0146-0500