SH7706 Datasheet, PDF (349/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
9.7 Cautions
1. CHCR_0 to CHCR_3 can be accessed in any data size. The DMA operation register
(DMAOR) must be accessed in byte (eight bits) or word (16 bits); other registers must be
accessed in word (16 bits) or longword (32 bits).
2. Before rewriting the RS0 to RS3 bits of CHCR_0 to CHCR_3, first clear the DE bit to 0 (when
rewriting CHCR, be sure to clear the DE bit to 0 in advance).
3. Even when the NMI interrupt is input when the DMAC is not operating, the NMIF bit of the
DMAOR will be set.
4. When entering the standby mode, the DME bit in DMAOR must be cleared to 0 and the
transfers accepted by the DMAC must end.
5. The on-chip peripherals which DMAC can access are SCIF, A/D converter, D/A converter,
and I/O ports. Do not access the other peripherals by DMAC.
6. When starting up the DMAC, set CHCR_0 to CHCR_3 or DMAOR last. Specifying other
registers last does not guarantee normal operation.
7. Even if the maximum number of transfers is performed in the same channel after the
DMATCR_0 to DMATCR_3 count reaches 0 and the DMA transfer ends normally, write 0 to
DMATCR_0 to DMATCR_3. Otherwise, normal DMA transfer may not be performed.
8. When using the address reload function, specify the burst mode as a transfer mode. In the
cycle-steal mode, normal DMA transfer may not be performed.
9. When using the address reload function, set the value multiple of four in DMATCR_0 to
DMATCR_3. Specifying other values does not guarantee normal operation.
10. When detecting an external request at the falling edge, keep the external request pin high when
setting the DMAC.
11. Do not access the space ranging from H'4000062 to H'400006F, which is not used in the
DMAC. Accessing that space may cause malfunctions.
12. The WAIT signal is ignored in the following cases:
A. In 16-byte DMA transfer or dual addressing mode, or when writing data to the external
address area
B. In 16-byte DMA transfer or single addressing mode, or when transferring data from an
external device with DACK to the external address area
13. When the DMAC transfers data under conditions (1) or (2) below, the CPU may fetch an
unexpected instruction, resulting in program runaway, or the DMA may transfer the wrong
data.
(1) At wake-up from the sleep mode when operating with a clock ratio for Iφ:Bφ of other than
1:1.
(2) The internal clock frequency division ratio bits (IFC[2:0]) in the frequency control register
(FRQCR) are modified.
Rev. 5.00 May 29, 2006 page 301 of 698
REJ09B0146-0500