SH7706 Datasheet, PDF (134/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 4 Exception Processing
Exception Type
Exception Event
General interrupt requests Nonmaskable interrupt
H-UDI interrupt
External hardware interrupts:
IRL3–IRL0 = 0000
IRL3–IRL0 = 0001
IRL3–IRL0 = 0010
IRL3–IRL0 = 0011
IRL3–IRL0 = 0100
IRL3–IRL0 = 0101
IRL3–IRL0 = 0110
IRL3–IRL0 = 0111
IRL3–IRL0 = 1000
IRL3–IRL0 = 1001
IRL3–IRL0 = 1010
IRL3–IRL0 = 1011
IRL3–IRL0 = 1100
IRL3–IRL0 = 1101
IRL3–IRL0 = 1110
Note: Exception codes H'120, H'140, and H'3E0 are reserved.
Exception Code
H'1C0
H'5E0
H'200
H'220
H'240
H'260
H'280
H'2A0
H'2C0
H'2E0
H'300
H'320
H'340
H'360
H'380
H'3A0
H'3C0
4.1.5 Exception Request and BL Bit
If a general exception event occurs when the BL bit in SR is 1, the CPU's internal registers are set
to their post-reset state, other module registers retain their contents prior to the general exception,
and a branch is made to the same address (H'A0000000) as for a reset.
If a general interrupt occurs when BL = 1, the request is masked (held pending) and not accepted
until the BL bit is cleared to 0 by software. For reentrant exception processing, the SPC and SSR
must be saved and the BL bit in SR cleared to 0.
4.1.6 Returning from Exception Processing
The RTE instruction is used to return from exception processing. When RTE is executed, the SPC
value is set in the PC, and the SSR value in SR, and the return from exception processing is
performed by branching to the SPC address.
Rev. 5.00 May 29, 2006 page 86 of 698
REJ09B0146-0500