SH7706 Datasheet, PDF (375/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 12 Timer Unit (TMU)
12.3.2 Timer Start Register (TSTR)
TSTR is an 8-bit read/write register that selects whether to run or halt the timer counters (TCNT_0
to TCNT_2) for channels 0 to 2. TSTR is initialized to H'00 by a power-on reset or manual reset,
but is not initialized in standby mode when the input clock selected for the channel is the on-chip
RTC clock (RTCCLK). It is initialized in standby mode, changing the multiplying ratio of PLL
circuit 1 or MSTP2 bit in STBCR is set to a logic one only when an external clock (TCLK) or the
peripheral clock (Pφ) is used as the input clock.
Bit Bit Name Initial Value R/W Description
7 to —
3
All 0
R
Reserved
These bits are always read 0. The write value should
always be 0.
2
STR2
0
R/W Counter Start 2
Selects whether to run or halt timer counter 2 (TCNT_2).
0: Halt TCNT_2 count
1: Start TCNT_2 counting
1
STR1
0
R/W Counter Start 1
Selects whether to run or halt timer counter 1 (TCNT_1).
0: Halt TCNT_1 count
1: Start TCNT_1 counting
0
STR0
0
R/W Counter Start 0
Selects whether to run or halt timer counter 0 (TCNT_0).
0: Halt TCNT_0 count
1: Start TCNT_0 counting
Rev. 5.00 May 29, 2006 page 327 of 698
REJ09B0146-0500